給一下程序?qū)懸粋€(gè)頂層模塊
/* 信號(hào)定義與說明：
CLK： 為同步時(shí)鐘；
EN： 使能信號(hào)，為1 的話，則控制器開始工作；
LAMPA： 控制A 方向四盞燈的亮滅；其中，LAMPA0~LAMPA3，分別控制A 方向的
左拐燈、綠燈、黃燈和紅燈；
LAMPB： 控制B 方向四盞燈的亮滅；其中，LAMPB0 ~ LAMPB3，分別控制B 方向的
左拐燈、綠燈、黃燈和紅燈；
ACOUNT： 用于A 方向燈的時(shí)間顯示，8 位，可驅(qū)動(dòng)兩個(gè)數(shù)碼管；
BCOUNT： 用于B 方向燈的時(shí)間顯示，8 位，可驅(qū)動(dòng)兩個(gè)數(shù)碼管。 */
module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT);
output[7:0] ACOUNT,BCOUNT;
output[3:0] LAMPA,LAMPB;
input CLK,EN;
reg[7:0] numa,numb;
reg tempa,tempb;
reg[2:0] counta,countb;
reg[7:0] ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft;
reg[3:0] LAMPA,LAMPB;
always @(EN)
if(!EN)
begin //設(shè)置各種燈的計(jì)數(shù)器的預(yù)置數(shù)
ared <=8'd60; //60 秒
ayellow <=8'd5; //5 秒
agreen <=8'd40; //40 秒
aleft <=8'd20; //20 秒
bred <=8'd60; //60 秒
byellow <=8'd5; //5 秒
bleft <=8'd20; //20 秒
bgreen <=8'd40; //40 秒
end
assign ACOUNT=numa;
assign BCOUNT=numb;
always @(posedge CLK) //該進(jìn)程控制A 方向的四種燈
begin
if(EN)
begin
if(!tempa)
begin
tempa<=1;
case(counta) //控制亮燈的順序
0: begin numa<=agreen; LAMPA<=2; counta<=1; end
1: begin numa<=ayellow; LAMPA<=4; counta<=2; end
2: begin numa<=aleft; LAMPA<=1; counta<=3; end
3: begin numa<=ayellow; LAMPA<=4; counta<=4; end
4: begin numa<=ared; LAMPA<=8; counta<=0; end
default: LAMPA<=8;
endcase
end
else begin //倒計(jì)時(shí)
if(numa>1)
if(numa[3:0]==0) begin
numa[3:0]<=4'b1001;
numa[7:4]<=numa[7:4]-1;
end
else numa[3:0]<=numa[3:0]-1;
if (numa==2) tempa<=0;
end
end
else begin
LAMPA<=4'b1000;
counta<=0; tempa<=0;
end
end
always @(posedge CLK) //該進(jìn)程控制B 方向的四種燈
begin
if (EN)
begin
if(!tempb)
begin
tempb<=1;
case (countb) //控制亮燈的順序
0: begin numb<=bred; LAMPB<=8; countb<=1; end
1: begin numb<=bgreen; LAMPB<=2; countb<=2; end
2: begin numb<=byellow; LAMPB<=4; countb<=3; end
3: begin numb<=bleft; LAMPB<=1; countb<=4; end
4: begin numb<=byellow; LAMPB<=4; countb<=0; end
default: LAMPB<=8;
endcase
end
else
begin //倒計(jì)時(shí)
if(numb>1)
if(!numb[3:0]) begin
numb[3:0]<=9;
numb[7:4]<=numb[7:4]-1;
end
else numb[3:0]<=numb[3:0]-1;
if(numb==2) tempb<=0;
end
end
else begin
LAMPB<=4'b1000;
tempb<=0; countb<=0;
end
end
endmodule
